Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGES

DECEMBER 1996

©1996 Integrated Device Technology, Inc

DSC-3545/-

SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• 8192 x 9-bit organization

• Pin/function compatible with IDT72421/722x1 family

• 15 ns read/write cycle time

• Read and write clocks can be independent

• Dual-Ported zero fall-through time architecture

• Empty and Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags can

be set to any depth

• Programmable Almost-Empty and Almost-Full flags

default to Empty+7, and Full-7, respectively

• Output enable puts output data bus in high-impedance

state

• Advanced submicron CMOS technology

• Available in 32-pin plastic leaded chip carrier (PLCC)

able, tested to military electrical specifications

DESCRIPTION:

The IDT72251 SyncFIFO

™ is a very high-speed, low-

power First-In, First-Out (FIFO) memory with clocked read

and write controls. The IDT72251 has a 8192 x 9-bit memory

array. This FIFO is applicable for a wide variety of data

buffering needs such as graphics, local area networks and

FUNCTIONAL BLOCK DIAGRAM

WCLK

WEN2

OFFSET REGISTER

INPUT REGISTER

RAM ARRAY

8192 x 9

WRITE CONTROL

LOGIC

WRITE POINTER

RESET LOGIC

OUTPUT REGISTER

RCLK

READ CONTROL

LOGIC

READ POINTER

FLAG

LOGIC

3545 drw 01

interprocessor communication.

This FIFO has a 9-bit input and output port. The input port

is controlled by a free-running clock (WCLK), and two write

enable pins (

WEN1, WEN2). Data is written into the

Synchronous FIFO on every rising clock edge when the write

enable pins are asserted. The output port is controlled by

another clock pin (RCLK) and two read enable pins (

REN1,

REN2). The read clock can be tied to the write clock for single

clock operation or the two clocks can run asynchronous of one

another for dual-clock operation. An output enable pin (

OE) is

provided on the read port for three-state control of the output.

The Synchronous FIFO has two fixed flags, Empty (

EF) and

Full (

FF). Two programmable flags, Almost-Empty (PAE) and

Almost-Full (

PAF), are provided for improved system control.

The programmable flags default to Empty+7 and Full-7 for

PAE and PAF, respectively. The programmable flag offset

loading is controlled by a simple state machine and is initiated

by asserting the load pin (

LD).

The IDT72251 is fabricated using IDT’s high-speed

submicron CMOS technology.

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

CMOS SyncFIFO

™

8192 X 9

ADVANCED

INFORMATION

IDT72251

5.14

1