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IDT72251 Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT72251 Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 17 page ![]() 5.14 9 IDT72251 CMOS SyncFIFO ™ 8192 x 9 COMMERCIAL TEMPERATURE RANGES NOTE: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge. Figure 6. Read Cycle Timing Figure 6. Read Cycle Timing tENH tENS NO OPERATION tOLZ VALID DATA tSKEW1 (1) tCLK tCLKH tCLKL tREF tREF tA tOE tOHZ RCLK REN1, REN2 EF Q0 - Q8 OE WCLK WEN1 WEN2 2655 drw 08 |
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