5.14

6

IDT72251 CMOS SyncFIFO

™

8192 x 9

COMMERCIAL TEMPERATURE RANGES

However, writing all offset registers does not have to occur

at one time. One or two offset registers can be written and then

by bringing the Write Enable 2/Load (WEN2/

LD) pin HIGH, the

FIFO is returned to normal read/write operation. When the

Write Enable 2/Load (WEN2/

LD) pin is set LOW, and Write

Enable 1 (

WEN1) is LOW, the next offset register in sequence

is written.

The contents of the offset registers can be read on the

output lines when the Write Enable 2/Load (WEN2/

LD) pin is

set low and both Read Enables (

REN1, REN2) are set LOW.

Data can be read on the LOW-to-HIGH transition of the read

clock (RCLK).

A read and write should not be performed simultaneously

to the offset registers.

LD

WEN1

Selection

0

0

Empty Offset (LSB)

Empty Offset (MSB)

Full Offset (LSB)

Full Offset (MSB)

0

1

No Operation

1

0

Write Into FIFO

1

1

No Operation

NOTE:

1. The same selection sequence applies to reading from the registers.

REN1

and

REN2 are enabled and read is performed on the LOW-to-HIGH

transition of RCLK.

Figure 2. Write Offset Register

72251 — 8192 x 9-BIT

87

0

Empty Offset (LSB)

Default Value 007H

84

0

(MSB)

00000

87

0

Full Offset (LSB)

Default Value 007H

84

0

(MSB)

00000

Figure 3. Offset Register Location and Default Values

NUMBER OF WORDS

IN FIFO

FF

PAF

PAE

EF

0H

H

L

L

HH

L

H

(n+1) to (8192-(m+1)

H

H

H

H

H

L

H

H

8192

L

L

H

H

TABLE 1: STATUS FLAGS

NOTES:

1. n = Empty Offset (n = 7 default value)

2. m = Full Offset (m = 7 default value)

OUTPUTS:

Full Flag (

FF

FF) — The Full Flag (FF) will go LOW, inhibiting

further write operation, when the device is full. If no reads are

performed after Reset (

RS), the Full Flag (FF) will go LOW

after 8192 writes for the IDT72251.

The Full Flag (

FF) is synchronized with respect to the LOW-

to-HIGH transition of the write clock (WCLK).

Empty Flag (

EF

EF) — The Empty Flag (EF) will go LOW,

inhibiting further read operations, when the read pointer is

equal to the write pointer, indicating the device is empty.

The Empty Flag (

EF) is synchronized with respect to the

LOW-to-HIGH transition of the read clock (RCLK).

Programmable Almost-Full Flag (

PAF

PAF) — The

Programmable Almost-Full Flag (

PAF) will go LOW when the

FIFO reaches the Almost-Full condition. If no reads are

performed after Reset (

RS), the Programmable Almost-Full

Flag (

PAF) will go LOW after 8192 writes for the IDT72251.

The offset “m” is defined in the Full offset registers.

If there is no Full offset specified, the Programmable

Almost-Full Flag (

PAF) will go LOW at Full-7 words.

The Programmable Almost-Full Flag (

PAF) is synchronized

with respect to the LOW-to-HIGH transition of the write clock

(WCLK).

Programmable Almost-Empty Flag (

PAE

PAE) — The

Programmable Almost-Empty Flag (

PAE) will go LOW when

the read pointer is "n+1" locations less than the write pointer.

The offset "n" is defined in the Empty offset registers. If no

reads are performed after Reset the Programmable Almost-

Empty Flag (

PAE) will go HIGH after "n+1" for the IDT72251.

If there is no Empty offset specified, the Programmable

Almost-Empty Flag (

PAE) will go LOW at Empty+7 words.

The Programmable Almost-Empty Flag (

PAE) is

synchronized with respect to the LOW-to-HIGH transition of

the read clock (RCLK).

data.