5.36

12

IDT72132, IDT72142

CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9

COMMERCIAL TEMPERATURE RANGES

2.

All other devices must have

FL in the high state.

3.

The Expansion Out (

XO) pin and Expansion In (XI) pin

of each device must be tied together.

4.

External logic is needed to generate a composite Full

Flag (

FF) and Empty Flag (EF). This requires the

OR-ing of all

EFs and OR-ing of all FFs (i.e., all must be

set to generate the correct composite

(FF) or (EF).

5.

The Retransmit (

RT) function and Half-Full Flag (HF)

are not available in the Depth Expansion mode.

TABLE 2: RESET AND FIRST LOAD TRUTH TABLE —

DEPTH EXPANSION/COMPOUND EXPANSION MODE

Inputs

Internal Status

Outputs

Mode

RS

FL/RT

XI

Read Pointer

Write Pointer

EF

FF

Reset-First

0

0

(1)

Location Zero

Location Zero

0

1

Device

Reset all

0

1

(1)

Location Zero

Location Zero

0

1

Other Devices

Read/Write

1

X

(1)

X

X

X

X

NOTES:

2752 tbl 10

1.

XI is connected to XO of the previous device.

2.

RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Ouput, FF = Full Flag Output, XI = Expansion Input.

Depth Expansion (Daisy Chain) Mode

The IDT72132/42 can be easily adapted to applications

where the requirements are for greater than 2048/4096 words.

Figure 15 demonstrates Depth Expansion using three

IDT72132/42. Any depth can be attained by adding additional

IDT72132/42 operates in the Depth Expansion configuration

when the following conditions are met:

1.

The first device must be designated by grounding the

First Load (

FL) control input.

Figure 15. An 8K x 8 Serial-In Parallel-Out FIFO

2752 drw 18

SICP

R

NW

SI

FIFO #1

IDT72142

SIX

FL/RT

XO

SICP

R

NW

SI

FIFO #2

IDT72142

SIX

FL/RT

XI

R

SI

SICP

XI

XO