Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGES

DECEMBER 1996

©1996 Integrated Device Technology, Inc.

DSC-2752/6

5.36

1

FEATURES:

•

35ns parallel-port access time, 45ns cycle time

•

50MHz serial port shift rate

•

Expandable in depth and width with no external

components

•

Programmable word lengths including 8, 9, 16-18, and

32-36 bit using Flexshift

™ serial input without using any

additional components

•

Multiple status flags: Full, Almost-Full (1/8 from full),

Half-Full, Almost Empty (1/8 from empty), and Empty

•

Asynchronous and simultaneous read and write

operations

•

Dual-Port zero fall-through architecture

•

Retransmit capability in single device mode

•

Produced with high-performance, low-power CMOS

technology

•

Available in the 28-pin plastic DIP

•

able, tested to military electrical specifications

DESCRIPTION:

The IDT72132/72142 are high-speed, low-power serial-to-

parallel FIFOs. These FIFOs are ideally suited to serial

communications applications, tape/disk controllers, and local

area networks (LANs). The IDT72132/72142 can be config-

ured with the IDTs parallel-to-serial FIFOs (IDT72131/72141)

for bidirectional serial data buffering.

The FIFO has a serial input port and a 9-bit parallel output

port. Wider and deeper serial-to-parallel data buffers can be

built using multiple IDT72132/72142 chips. IDTs unique

Flexshift serial expansion logic (SIX,

NW) makes width

expansion possible with no additional components. These

FIFOs will expand to a variety of word widths including 8, 9, 16,

and 32 bits. The IDT72132/142 can also be directly connected

for depth expansion.

Five flags are provided to monitor the FIFO. The full and

empty flags prevent any FIFO data overflow or underflow

conditions. The Almost-Full (7/8), Half-Full, and Almost Empty

(1/8) flags signal memory utilization within the FIFO.

The IDT72132/72142 is fabricated using IDTs high-speed

submicron CMOS technology.

IDT72132

IDT72142

CMOS SERIAL-TO-PARALLEL FIFO

2048 x 9

4096 x 9

FUNCTIONAL BLOCK DIAGRAM

2752 drw 01

RAM ARRAY

2048 x 9

4096 x 9

NEXT WRITE

POINTER

READ

POINTER

FLAG

LOGIC

EF

AEF

/HF

FF

R

8

NW

RESET

LOGIC

RS

EXPANSION

LOGIC

XI

FL/RT

XO/

SERIAL INPUT

CIRCUITRY

SICP

SIX

SI

OE

PIN CONFIGURATION

5

6

7

8

9

10

11

12

FF

NW

1

2

3

4

26

25

24

23

22

21

20

19

Vcc

18

17

16

15

P28-1

&

C28-3

XI

SIX

FL/RT

RS

EF

XO/HF

SICP

SI

AEF

GND

13

14

28

27

GND

OE

2752 drw 02

GND

R

DIP

TOP VIEW

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.