5.36

7

IDT72132, IDT72142

CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9

COMMERCIAL TEMPERATURE RANGES

NOTE:

1. After

FF goes LOW and the last bit of the final word has been clocked in, SICP should not be clocked until FF goes HIGH.

Figure 5. Full Flag from Last Write to First Read

Figure 6. Empty Flag from Last Read to First Write

2752 drw 08

SICP

LAST WRITE

NO WRITE

FIRST READ

ADDITIONAL

READS

FIRST WRITE

0

1

n – 1

0

1

n – 1

R

FF

(1)

2752 drw 09

SICP

LAST READ

IGNORED

READ

FIRST WRITE

ADDITIONAL

WRITES

FIRST READ

0

1

n – 1

0

1

n – 1

R

EF

VALID

VALID

2752 drw 10

SICP

0

1

n – 1

R

EF

0

1

n – 1

0

FIRST SERIAL-IN WORD

SECOND SERIAL-IN WORD

Figure 7. Empty Boundry Condition Timing