5.36

5

IDT72132, IDT72142

CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9

COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

5ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figure A

2752 tbl 08

Figure 1. Reset

NOTE:

FUNCTIONAL DESCRIPTION

Serial Data Input

The serial data is input on the SI pin. The data is clocked

in on the rising edge of SICP providing the Full Flag (

FF) is not

asserted. If the Full Flag is asserted then the next parallel data

word is inhibited from moving into the RAM array. NOTE:

SICP should not be clocked once the last bit of the last word

has been shifted in, as indicated by

NW HIGH and FF LOW.

If it is, then the input data will be lost.

The serial word is shifted in Least Significant Bit first. Thus,

when the FIFO is read, the Least Significant Bit will come out

width must be programmed by connecting the appropriate

NW input. The data set lines are

taps off a digital delay line. Selecting one of these taps

programs the width of the serial word to be written in.

*Includies jig and scope capacitances

Figure A. Output Load

or equivalent circuit

1.1K

Ω

30pF*

680

Ω

5V

D.U.T.

2752 drw 03

2752 drw 04

R

RS

AEF, EF

HF, FF

SICP

D ,D

78

0

n-1

(1)

Parallel Data Output

A read cycle is initiated on the falling edge of Read (

R)

provided the Empty Flag is not set. The output data is

accessed on a first-in/first-out basis, independent of the

falling edge of

R and the output bus Q goes into high imped-

ance after

R goes HIGH.

Alternately, the user can access the FIFO by keeping

R

LOW and enabling data on the bus by asserting Output Enable

(

OE). When R is LOW, the OE signal enables data on the

output bus. When

R is LOW and OE is HIGH, the output bus

is three-stated. When

R is HIGH, the output bus is disabled

irrespective of

OE.