IDT72131 datasheet(10/13 Pages) IDT

Part #	IDT72131

Description	CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9

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Manufacturer	IDT [Integrated Device Technology]

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10 / 13 page

5.34

10

IDT72131, IDT72141

CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9

COMMERCIAL TEMPERATURE RANGES

OPERATING CONFIGURATIONS

Single Device Configuration

In the standalone case, the SOX line is tied HIGH and not

used. On the first LOW-to-HIGH of the SOCP clock, all of the

Data Set lines (Q4, Q6, Q7, Q8) go LOW and a new serial word

is started. The Data Set lines then go HIGH on the equivalent

SOCP clock pulse. This continues until the Q line connected

to

NR goes HIGH completing the serial word. The cycle is then

repeated with the next LOW-to-HIGH transition of SOCP.

Figure 12. Eight-Bit Word Single Device Configuration

TRUTH TABLES

TABLE 1: RESET AND RETRANSMIT —

SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE

Inputs

Internal Status

Outputs

Mode

RS

FL/RT

XI

Read Pointer

Write Pointer

AEF, EF

FF

HF

Reset

0

X

0

Location Zero

0

1

Retransmit

1

0

Location Zero

Unchanged

X

Read/Write

1

0

Increment

(1)

Increment

(1)

XX

X

NOTE:

2751 tbl 09

1. Pointer will increment if appropriate flag is HIGH.

2751 drw 15

SOCP

NR

V CC

01

23

4

5

67

01

2

3

4

5

6

7

0

Q 4

Q 6

Q 7

SOCP

SOX

SERIAL OUTPUT CLOCK

SO

XI

SERIAL DATA OUTPUT

GND

PARALLEL DATA IN

D 0-7

NR

Q 4

Q 6 Q 7 Q8

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IDT72131 Datasheet(PDF) 10 Page - Integrated Device Technology

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