5.34

7

IDT72131, IDT72141

CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9

COMMERCIAL TEMPERATURE RANGES

NOTE:

1. Once

EF has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until EF goes HIGH.

NOTE:

1. SOCP should not be clocked until

EF goes HIGH.

Figure 6. Empty Boundary Condition Timing

2751 drw 09

SOCP

0

1

n – 1

W

EF

SO

(1)

Figure 5. Empty Flag from Last Read to First Write

2751 drw 08

SOCP

LAST READ

NO READ

FIRST WRITE

ADDITIONAL

WRITES

FIRST READ

0

1

n – 1

0

1

n – 1

W

EF

SO

VALID

VALID

(1)