5.34

5

IDT72131, IDT72141

CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9

COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

5ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figure A

2751 tbl 08

or equivalent circuit

Figure 1. Reset

Serial Data Output

The serial data is output on the SO pin. The data is clocked

out on the rising edge of SOCP providing the Empty Flag (

EF)

is not asserted. If the Empty Flag is asserted then the next data

word is inhibited from moving to the output register and being

clocked out by SOCP. NOTE: SOCP should not be clocked

once the last bit of the last word has been clocked out. If it is,

then two things will occur. One, the SO pin will go High-Z and

two, SOCP will be out of sync with Next Read (

NR).

The serial word is shifted out Least Significant Bit first, that

is the first bit will be D0, then D1 and so on up to the serial word

width. The serial word width must be programmed by connect-

ing the appropriate Data Set line (Q4, Q6, Q7 or Q8) to the

NR

input. The Data Set lines are taps off a digital delay line.

Selecting one of these taps, programs the width of the serial

word to be read and shifted out.

FUNCTIONAL DESCRIPTION

Parallel Data Input

The data is written into the FIFO in parallel through the

edge of the Write (

W) signal provided the Full Flag (FF) is not

asserted. If the

W signal changes from HIGH-to-LOW and the

Full-Flag (

FF) is already set, the write line is inhibited internally

from incrementing the write pointer and no write operation

occurs.

Data set-up and hold times must be met with respect to the

rising edge of Write. The data is written to the RAM at the write

pointer. On the rising edge of

W, the write pointer is

incremented. Write operations can occur simultaneously or

asynchronously with read operations.

*Including jig and scope capacitances

Figure A. Ouput Load

1.1K

Ω

30pF*

680

Ω

5V

D.U.T.

2751 drw 03

2751 drw 04

W

RS

AEF, EF

HF, FF

SOCP