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IDT72131 Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT72131 Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 13 page 5.34 4 IDT72131, IDT72141 CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9 COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C) Commercial IDT72131L35 IDT72131L50 IDT72141L35 IDT72141L50 Symbol Parameter Min. Max. Min. Max. Unit tS Parallel Shift Frequency — 22.2 — 15 MHz tSOCP Serial-Out Shift Frequency — 50 — 40 MHz PARALLEL INPUT TIMINGS tDS Data Set-up Time 18 — 30 — ns tDH Data Hold Time 0 — 5 — ns tWC Write Cycle Time 45 — 65 — ns tWPW Write Pulse Width 35 — 50 — ns tWR Write Recovery Time 10 — 15 — ns tWEF Write High to EF HIGH — 30 — 45 ns tWFF Write Low to FF LOW — 30 — 45 ns tWF Write Low to Transitioning HF, AEF —45 — 65 ns tWPF Write Pulse Width After FF HIGH 35 — 50 — ns SERIAL OUTPUT TIMINGS tSOHZ SOCP Rising Edge to SO at High-Z(1) 516 5 26 ns tSOLZ SOCP Rising Edge to SO at Low-Z(1) 522 5 22 ns tSOPD SOCP Rising Edge to Valid Data on SO — 18 — 18 ns tSOX SOX Set-up Time to SOCP Rising Edge 5 — 5 — ns tSOCW Serial In Clock Width HIGH/LOW 8 — 10 — ns tSOCEF SOCP Rising Edge (Bit 0 - Last Word) to EF LOW — 20 — 25 ns tSOCFF SOCP Rising Edge to FF HIGH — 30 — 40 ns tSOCF SOCP Rising Edge to HF, AEF, HIGH — 30 — 40 ns tREFSO Recovery Time SOCP After EF HIGH 35 — 50 — ns RESET TIMINGS tRSC Reset Cycle Time 45 — 65 — ns tRS Reset Pulse Width 35 — 50 — ns tRSS Reset Set-up Time 35 — 50 — ns tRSR Reset Recovery Time 10 — 15 — ns tRSF1 Reset to EF and AEF LOW — 45 — 65 ns tRSF2 Reset to HF and FF HIGH — 45 — 65 ns tRSQL Reset to Q LOW 20 — 35 — ns tRSQH Reset to Q HIGH 20 — 35 — ns RETRANSMIT TIMINGS tRTC Retransmit Cycle Time 45 — 65 — ns tRT Retransmit Pulse Width 35 — 50 — ns tRTS Retransmit Set-up Time 35 — 50 — ns tRTR Retransmit Recovery Time 10 — 15 — ns DEPTH EXPANSION MODE TIMINGS tXOL Read/Write to XO LOW — 35 — 50 ns tXOH Read/Write to XO HIGH — 35 — 50 ns tXI XI Pulse Width 35 — 50 — ns tXIR XI Recovery Time 10 — 10 — ns tXIS XI Set-up Time 15 — 15 — ns NOTE: 2751 tbl 07 1. Guaranteed by design minimum times, not tested. |
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