6.35

10

IDT70V05S/L

HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM

COMMERCIAL TEMPERATURE RANGE

BUSY TIMING (M/

BUSY Input to Write

(4)

0—

0

—

0

—

ns

Write Hold After

20

—

25

—

25

—

ns

PORT-TO-PORT DELAY TIMING

Write Pulse to Data Delay

(1)

—55

—

65

—

85

ns

Write Data Valid to Read Data Delay

(1)

—50

—

60

—

80

ns

AC ELECTRICAL CHARACTERISTICS OVER THE

IDT70V05X25

IDT70V05X35

IDT70V05X55

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

BUSY TIMING (M/

BUSY Access Time from Address Match

—

25

—

35

—

45

ns

BUSY Disable Time from Address Not Matched

—

25

—

35

—

45

ns

BUSY Access Time from Chip Enable Low

—

25

—

35

—

45

ns

BUSY Disable Time from Chip Enable High

—

25

—

35

—

45

ns

Arbitration Priority Set-up Time

(2)

5—

5

—

5

—

ns

—35

—

40

—

50

ns

Write Hold After

20

—

25

—

25

—

ns

2941 drw 13

MATCH

R/

VALID

(1)

MATCH

VALID

(3)

NOTES:

2941 tbl 13

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With

of Write With Port-To-Port Delay (M/

2. To ensure that the earlier of the two ports wins.

4. To ensure that the write cycle is inhibited during contention.

5. To ensure that a write cycle is completed after contention.

6. "X" is part numbers indicates power rating (S or L).

TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ WITH BUSY (M/

NOTES:

2.

3.

4. If M/

5. All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from port "A".