Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

OCTOBER 1996

©1996 Integrated Device Technology, Inc.

DSC-2941/3

IDT70V05S/L

HIGH-SPEED 3.3V

8K x 8 DUAL-PORT

STATIC RAM

FEATURES:

• True Dual-Ported memory cells which allow simulta-

neous access of the same memory location

• High-speed access

— Commercial: 25/35/55ns (max.)

• Low-power operation

— IDT70V05S

Active: 350mW (typ.)

Standby: 3.5mW (typ.)

— IDT70V05L

Active: 350mW (typ.)

Standby: 1mW (typ.)

• IDT70V05 easily expands data bus width to 16 bits or

more using the Master/Slave select when cascading

more than one device

•M/

S = H for BUSY output flag on Master

M/

S = L for BUSY input on Slave

• Busy and Interrupt Flags

• On-chip port arbitration logic

• Full on-chip hardware support of semaphore signaling

between ports

• Fully asynchronous operation from either port

• Devices are capable of withstanding greater than 2001V

electrostatic discharge

• Battery backup operation—2V data retention

•

LVTTL-compatible, single 3.3V (

±0.3V) power supply

• Available in 68-pin PGA, 68-pin PLCC, and a 64-pin

TQFP

DESCRIPTION:

The IDT70V05 is a high-speed 8K x 8 Dual-Port Static

RAM. The IDT70V05 is designed to be used as a stand-alone

Dual-Port RAM or as a combination MASTER/SLAVE Dual-

Port RAM for 16-bit-or-more word systems. Using the IDT

MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider

memory system applications results in full-speed, error-free

FUNCTIONAL BLOCK DIAGRAM

NOTES:

1. (MASTER):

BUSY is output;

(SLAVE):

BUSY

is input.

2. BUSY outputs

and INT outputs

are non-tri-

stated push-pull.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

1

6.35

I/O

Control

Address

Decoder

MEMORY

ARRAY

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

Address

Decoder

I/O

Control

R/

2941 drw 01

R/

M/

S

(2)

(1,2)

(1,2)

(2)

R/

R/

13

13

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.