6.35

8

IDT70V05S/L

HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/

W

W

W

W

R/

W

(2)

OE

ADDRESS

CE or SEM

(6)

(4)

(4)

(3)

2941 drw 09

(7)

(7)

(9)

NOTES:

1. R/

W or CE must be HIGH during all address transitions.

CE and a LOW R/W for memory array writing cycle.

CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the

CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last,

CE, or R/W.

7. Timing depends on which enable signal is de-asserted first,

CE, or R/W.

8. If

OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can

2941 drw 10

ADDRESS

R/

W

(3)

(2)

(6)

(9)

TIMING WAVEFORM OF WRITE CYCLE NO. 2,

CE

CE

CE

CE