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IDT70V05S Datasheet(PDF) 7 Page - Integrated Device Technology

Part # IDT70V05S
Description  HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT70V05S Datasheet(HTML) 7 Page - Integrated Device Technology

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IDT70V05S/L
HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
6.35
7
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(5)
IDT70V05X25
IDT70V05X35
IDT70V05X55
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time
25
35
55
ns
tEW
Chip Enable to End-of-Write
(3)
20
30
45
ns
tAW
Address Valid to End-of-Write
20
30
45
ns
tAS
Address Set-up Time
(3)
0—
0
0
ns
tWP
Write Pulse Width
20
25
40
ns
tWR
Write Recovery Time
0
0
0
ns
tDW
Data Valid to End-of-Write
15
20
30
ns
tHZ
Output High-Z Time
(1, 2)
—15
20
25
ns
tDH
Data Hold Time
(4)
0—
0
0
ns
tWZ
Write Enable to Output in High-Z
(1, 2)
—15
20
25
ns
tOW
Output Active from End-of-Write
(1, 2, 4)
0—
0
0
ns
tSWRD
SEM Flag Write to Read Time
5
5
5
ns
tSPS
SEM Flag Contention Window
5
5
5
ns
WAVEFORM OF READ CYCLES(5)
tRC
R/
W
CE
ADDR
tAA
OE
2941 drw 08
(4)
tACE
(4)
tAOE
(4)
(1)
tLZ
tOH
(2)
tHZ
(3, 4)
tBDD
DATAOUT
BUSYOUT
VALID DATA
(4)
NOTES:
1. Timing depends on which signal is asserted last,
OE or CE.
2. Timing depends on which signal is de-asserted first,
CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5.
SEM = VIH.
NOTES:
2941 tbl 12
1. Transition is measured
±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but not production tested.
3. To access RAM,
CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary
over voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. "X" in part numbers indicates power rating (S or L).


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