IDT7005S/L

HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.06

17

The use of busy logic is not required or desirable for all

applications. In some cases it may be useful to logically OR

the busy outputs together and use any busy indication as an

interrupt source to flag the event of an illegal or illogical

operation. If the write inhibit function of busy logic is not

desirable, the busy logic can be disabled by placing the part

in slave mode with the M/

S pin. Once in slave mode the BUSY

pin operates solely as a write inhibit input pin. Normal opera-

tion can be programmed by tying the

BUSY pins high. If

desired, unintended write operations can be prevented to a

port by tying the busy pin for that port low.

The busy outputs on the IDT 7005 RAM in master mode,

are push-pull type outputs and do not require pull up resistors

to operate. If these RAMs are being expanded in depth, then

the busy indication for the resulting array requires the use of

an external AND gate.

WIDTH EXPANSION WITH BUSY LOGIC

MASTER/SLAVE ARRAYS

When expanding an IDT7005 RAM array in width while

using busy logic, one master part is used to decide which side

of the RAM array will receive a busy indication, and to output

that indication. Any number of slaves to be addressed in the

same address range as the master, use the busy signal as a

write inhibit signal. Thus on the IDT7005 RAM the busy pin is

an output if the part is used as a master (M/

S pin = H), and the

busy pin is an input if the part used as a slave (M/

S pin = L) as

shown in Figure 3.

If two or more master parts were used when expanding in

width, a split decision could result with one master indicating

busy on one side of the array and another master indicating

busy on one other side of the array. This would inhibit the write

operations from one port for part of a word and inhibit the write

operations from the other port for the other part of the word.

The busy arbitration, on a master, is based on the chip

enable and address signals only. It ignores whether an access

is a read or write. In a master/slave array, both address and

chip enable must be valid long enough for a busy flag to be

Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7005 RAMs.

output from the master before the actual write pulse can be

initiated with the R/

W signal. Failure to observe this timing can

result in a glitched internal write inhibit signal and corrupted

data in the slave.

SEMAPHORES

The IDT7005 is an extremely fast Dual-Port 8K x 8 CMOS

Static RAM with an additional 8 address locations dedicated

to binary semaphore flags. These flags allow either processor

on the left or right side of the Dual-Port RAM to claim a

privilege over the other processor for functions defined by the

system designer’s software. As an example, the semaphore

can be used by one processor to inhibit the other from

accessing a portion of the Dual-Port RAM or any other shared

resource.

The Dual-Port RAM features a fast access time, and both

ports are completely independent of each other. This means

that the activity on the left port in no way slows the access time

of the right port. Both ports are identical in function to standard

CMOS Static RAM and can be read from, or written to, at the

same time with the only possible conflict arising from the

simultaneous writing of, or a simultaneous READ/WRITE of,

a non-semaphore location. Semaphores are protected against

such ambiguous situations and may be used by the system

program to avoid any conflicts in the non-semaphore portion

of the Dual-Port RAM. These devices have an automatic

power-down feature controlled by

CE, the Dual-Port RAM

enable, and

SEM, the semaphore enable. The CE and SEM

pins control on-chip power down circuitry that permits the

respective port to go into standby mode when not selected.

This is the condition which is shown in Truth Table where

CE

and

SEM are both high.

Systems which can best use the IDT7005 contain multiple

processors or controllers and are typically very high-speed

systems which are software controlled or software intensive.

These systems can benefit from a performance increase

offered by the IDT7005's hardware semaphores, which pro-

vide a lockout mechanism without requiring complex pro-

gramming.

2738 drw 19

MASTER

Dual Port

RAM

CE

MASTER

Dual Port

RAM

CE

SLAVE

Dual Port

RAM

CE

SLAVE

Dual Port

RAM

CE