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IDT7005S Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT7005S Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 20 page 6.06 8 IDT7005S/L HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES WAVEFORM OF READ CYCLES(5) NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first, CE or OE. 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD. 5. SEM = VIH. CE 2738 drw 08 tPU ICC ISB tPD 50% 50% tRC R/ W CE ADDR tAA OE 2738 drw 07 (4) tACE (4) tAOE (4) (1) tLZ tOH (2) tHZ (3, 4) tBDD DATAOUT BUSYOUT VALID DATA (4) TIMING OF POWER-UP POWER-DOWN |
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