IDT7005S/L

HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.06

7

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

5ns Max.

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

Figure 1 and 2

2738 tbl 12

IDT7005X35

IDT7005X55

IDT7005X70

Mil. Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

Read Cycle Time

35

—

55

—

70

—

ns

Address Access Time

—

35

—

55

—

70

ns

Chip Enable Access Time

(3)

—35—55

—70

ns

Output Enable Access Time

—

20

—

30

—

35

ns

Output Hold from Address Change

3

—

3

—

3

—

ns

Output Low-Z Time

(1, 2)

3—

3—

3—

ns

Output High-Z Time

(1, 2)

—15—25

—30

ns

Chip Enable to Power Up Time

(2)

0—

0—

0—

ns

Chip Disable to Power Down Time

(2)

—35—50

—50

ns

Semaphore Flag Update Pulse (

OE or SEM)

15—15

—15—

ns

Semaphore Address Access Time

—

35

—

55

—

70

ns

NOTES:

2738 tbl 13

1. Transition is measured

±500mV from Low or High-impedance voltage with Output Test Load (Figures 2).

2. This parameter is guaranteed by device characterization but not production tested.

3. To access RAM,

4. "X" in part numbers indicates power rating (S or L).

1250

Ω

30pF

775

Ω

BUSY

INT

5V

5V

1250

Ω

5pF

775

Ω

2738 drw 06

Figure 1. AC Output Test Load

Figure 2. Output Load

Including scope and jig

AC ELECTRICAL CHARACTERISTICS OVER THE

IDT7005X15

IDT7005X17

IDT7005X20

IDT7005X25

Com'l. Only

Com'l. Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

Read Cycle Time

15

—

17

—

20

—

25

—

ns

Address Access Time

—

15

—

17

—

20

—

25

ns

Chip Enable Access Time

(3)

—

15

—

17

—

20

—

25

ns

Output Enable Access Time

—

10

—

10

—

12

—

13

ns

Output Hold from Address Change

3

3

—

3

—

3

—

ns

Output Low-Z Time

(1, 2)

3

—

3

—

3

—

3

—

ns

Output High-Z Time

(1, 2)

10

—

10

—

12

—

15

ns

Chip Enable to Power Up Time

(2)

0

0

—

0

—

0

—

ns

Chip Disable to Power Down Time

(2)

15

—

17

—

20

—

25

ns

Semaphore Flag Update Pulse (

OE or SEM)

10

10

—

10

—

10

—

ns

Semaphore Address Access Time

15

—

17

—

20

—

25

ns