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GM71C17800C Datasheet(PDF) 4 Page - Hynix Semiconductor |
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GM71C17800C Datasheet(HTML) 4 Page - Hynix Semiconductor |
4 / 9 page GM71C17800C GM71CS17800CL Rev 0.1 / Apr’01 Capacitance (VCC = 5V+/-10%, TA = 25C) Symbol Parameter Note CI1 CI2 CI/O Input Capacitance (Address) Input Capacitance (Clocks) Output Capacitance (Data-In/Out) 1 1 1, 2 Unit pF pF pF Max 5 7 7 Min - - - Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable DOUT. AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ +70C, Vss = 0V, Note 1, 2, 18) Test Conditions Input rise and fall times : 5 ns Output timing reference levels : 0.4V, 2.4V Input timing reference levels : 0.8V, 2.4V Output load : 2TTL gate + CL (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Symbol Parameter Note Max Unit Min Max Min Max Min tRC Random Read or Write Cycle Time 90 - 110 - 130 - tRP RAS Precharge Time 30 - 40 - 50 - tRAS RAS Pulse Width 50 10,000 60 10,000 70 10,000 tCAS CAS Pulse Width 10,000 10,000 10,000 15 18 tASR Row Address Set up Time 0 - - - 0 0 tRAH Row Address Hold Time 7 - - - 10 10 tASC Column Address Set-up Time 0 - - - 0 0 tCAH Column Address Hold Time - - - 10 15 tRCD RAS to CAS Delay Time 17 45 45 52 20 20 3 tRAD RAS to Column Address Delay Time 12 30 30 35 15 15 4 tRSH RAS Hold Time 13 - - - 15 18 tCSH CAS Hold Time 50 - - - 60 70 tCRP CAS to RAS Precharge Time 5 - - - 5 5 tT Transition Time (Rise and Fall) 3 50 50 50 3 3 7 tDZO OE Delay Time from DIN 0 - - - 0 0 tDZC CAS Delay Time from DIN 0 - - - 0 0 GM71C(S)17800 C/CL-5 OE to DIN Delay Time 13 - - - 15 18 5 6 6 tCP CAS Precharge Time 7 - 10 - 10 - tODD GM71C(S)17800 C/CL-6 GM71C(S)17800 C/CL-7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 7 |
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