© 2002 Fairchild Semiconductor Corporation

www.fairchildsemi.com

LM555 Rev. 1.1.0

5

1. Monostable Operation

Figure 2 illustrates a monostable circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage

the timer's internal flip-flop turns the discharging transistor off and causes the timer output to become high by charging

the external capacitor C1 and setting the flip-flop output at the same time.

width.

flop, turning the discharging transistor on. At this time, C1 begins to discharge and the timer output converts to low.

In this way, the timer operating in the monostable repeats the above process. Figure 3 shows the time constant rela-

the timer output turns low. That is, although the output remains unaffected even if a different trigger pulse is applied

while the output is high, it may be affected and the waveform does not operate properly if the trigger pulse voltage at

2. Astable Operation

Figure 5. Waveforms of Monostable Operation

(abnormal)

Figure 6. A Stable Circuit

Figure 7. Capacitance and Resistance vs. Frequency

1

5

6

7

8

4

2

3

RESET

Vcc

DISCH

THRES

CONT

GND

OUT

TRIG

+Vcc

C1

C2

100m

1

10

100

1k

10k

100k

1E-3

0.01

0.1

1

10

100

(R

Frequency(Hz)