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AT42QT1111-AU Datasheet(PDF) 38 Page - ATMEL Corporation |
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AT42QT1111-AU Datasheet(HTML) 38 Page - ATMEL Corporation |
38 / 50 page ![]() 38 AT42QT1111-MU / AT42QT1111-AU [DATASHEET] 9571C–AT42–05/2013 8.4 Timing Specifications 8.5 SPI Bus Specifications 8.5.1 General Specifications 8.5.2 Full SPI Mode Parameter Description Min Typ Max Units Notes TBS Burst duration – 6 – ms 4.7 nF Cs / parallel acquisition Fc Burst center frequency – 40 – kHz Fm Burst modulation, percentage – 18 – % TPW Pulse width – 9000 – ns Parameter Specification Address space 8-bit Maximum clock rate 750 KHz Minimum low clock period 666 ns Minimum high clock period 666 ns Clock idle High Setup on Leading (falling) edge Clock out on Trailing (rising) edge SPI Enable delay (SS low to SCK low) 1 µs minimum Parameter Specification Minimum time between bytes 300 µs Minimum time between communications Generally 300 µs; longer delays required to implement some commands, as follows: Send Setups: 300 µs after all setup bytes are returned Calibrate All: 300 µs Calibrate Key: 300 µs Reset: 320 ms Sleep: 300 µs after a low signal is applied to SS or CHANGE to wake the device Store to EEPROM: 200 ms Restore from EEPROM: 150 ms Erase EEPROM: 50 ms Recover EEPROM: 50 ms |
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