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AT42QT1111-AU Datasheet(PDF) 30 Page - ATMEL Corporation |
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AT42QT1111-AU Datasheet(HTML) 30 Page - ATMEL Corporation |
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30 / 50 page  30 AT42QT1111-MU / AT42QT1111-AU [DATASHEET] 9571C–AT42–05/2013 7.6 Address 2: Detect Integrator Limit (DIL)/Drift Hold Time (DHT) DIL: the detection integrator (DI) limit. To suppress false detections caused by spurious events like electrical noise, the device incorporates a DI counter mechanism. A per-key counter is incremented each time the channel has exceeded its threshold and stayed there for a number of acquisitions in succession, without going below the threshold level. When this counter reaches a preset limit the channel is finally declared to be touched. If on any acquisition the delta is not seen to exceed the threshold level, the counter is cleared and the process has to start from the beginning. Similarly, when a touch is removed the key is counted out of touch by the DI counter. Note: A setting of 0 for DI is invalid; the valid range is 1 to 15. DHT: the drift hold time. After a key-touch has been removed, the QT1111 pauses in the implementation of its “Drift” compensation for a time. After this time has expired, drift compensation continues as normal. The drift timer continues from the value at which it was “paused” at the start of the Drift Hold Time. The Drift Hold Time is a multiple of 160 ms, providing options from 0 to 2400 ms. Default DIL value: 3 Default DHT value: 8 (1280 ms) 7.7 Address 3: Positive Threshold (PTHR)/Positive Hysteresis (PHYST) PTHR: the positive threshold for the signal. If a key signal is significantly higher than the reference signal, this typically indicates that the calibration data is no longer valid. In other words, some factor has changed since the calibration was carried out, thus rendering it invalid. Generally this is compensated for by the drift, but the greater the difference the longer this will take. In order to speed up this correction, the positive threshold is used: if the positive threshold is exceeded, the QT1111 (that is, all keys) is recalibrated. PHYST: positive hysteresis. This setting provides a greater degree of control over the implementation of the positive threshold recalibration. The positive hysteresis operates as a “modifier” for the positive threshold. When a key signal is detected as being over the positive threshold, the positive threshold is reduced by a factor corresponding to the positive hysteresis so that the key will not go in and out of positive detection when the signal is on the borderline between drift-compensation of a positive error or recalibration. The settings for positive hysteresis are: 00 = No change to positive threshold 01 = 12.5% reduction in positive-detect threshold 10 = 25% reduction in positive-detect threshold 11 = 37.5% reduction in positive-detect threshold Default PTHR value: 4 (4 counts above reference) Default PHYST value: 2 (25% positive hysteresis) Table 7-4. Detect Integrator/Drift Hold Time Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2 DIL DHT Table 7-5. Positive Threshold (THR)/Positive Hystereis (HYST) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3 PTHR PHYST |
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