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AT42QT1111-AU Datasheet(PDF) 16 Page - ATMEL Corporation |
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AT42QT1111-AU Datasheet(HTML) 16 Page - ATMEL Corporation |
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16 / 50 page  16 AT42QT1111-MU / AT42QT1111-AU [DATASHEET] 9571C–AT42–05/2013 Byte 0 is a counter that increments from 0 to 254 on successive exchanges to confirm that firmware is operating correctly. Bytes 1 – 3 indicate the detect status of channels 0 – 3, 4 – 7 and 8 – 10 respectively (two bits per channel), as follows: 00 = Channel not in detect 01 = Channel in detect 10 = Not Allowed 11 = Invalid Signal (Channel disabled) Bytes 4 – 6 indicate the error status of channels 0 – 3, 4 – 7 and 8 – 10 respectively (two bits per channel), as follows: 00 = No error 01 = Not allowed 10 = Error on channel 11 = Invalid signal (channel disabled) Successive byte exchanges in Quick SPI mode cycle through the 7 bytes of status information. If synchronization is lost, the host must either re-synchronize by identifying the incrementing counter byte (byte 0) or pausing communications for at least 100 ms so the QT1111 will reset its SPI state. 4.1.6.3 Commands in Quick SPI Mode Only two host commands are recognized under Quick SPI mode. These are shown in Table 4-2. CRC checking is not implemented in Quick SPI mode for host commands or return data. 4.1.6.4 Quick SPI Mode timing In Quick SPI mode, the minimum time between byte exchanges is reduced to 100 µS. If a pause in communications of 100 ms is detected during reading of the 7-byte report, the QT1111 resets the exchange, and on the next byte read it returns byte 0 of the report. 4.2 Reset The QT1111 can be reset using one of two methods: Hardware reset: An external reset logic line can be used if desired, fed into the RESET pin. However, under most conditions it is acceptable to tie RESET to Vdd. Software reset: A software reset can be forced using the “Reset” control command. For both methods, the device will follow the same initialization sequence. If there any saved settings in the EEPROM, these are loaded into RAM. Otherwise the default settings are applied. Note: The SPI interface becomes active after the QT1111 has completed its startup sequence, taking approximately 320 ms after power on/reset. Table 4-2. Host Commands in Quick SPI Mode Command Code Purpose Store to EEPROM 0x0A Allows for “Quick SPI mode” to be stored as the default start-up mode Enable Full SPI 0x36 Enables full SPI mode |
Similar Part No. - AT42QT1111-AU_14 |
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Similar Description - AT42QT1111-AU_14 |
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