13

AT42QT2100 [DATASHEET]

9554E–AT42–01/13

See

Section 6.5 on page 32 for details of the SPI Configuration and Timing Parameters.

The host must always transfer three bytes in succession within the allotted time (10 ms maximum). If all bytes are

not received in this interval it is treated by the QT2100 as an error. In this case the exchange is reset and the next

read will contain the first data byte of a new exchange.

Messages from the host to the QT2100 carry configuration information; return data from the QT2100 carries key

state information. For details of the message contents see

Section 5. on page 19.

Figure 6-1 and Figure 6-2 on page 33 show the basic timing for SPI operation. The host does the clocking and

controls the timing of the transfers from the QT2100. Transfers are always clocked as a set of three bytes, Byte 1, 2,

and 3.

DRDY stays high for 500

µs. It falls again after Byte 3 has shifted to indicate completion. DRDY goes high after each

burst.

After the host asserts SS low, it should wait >22

µs in low power mode before starting SCK; in Free run mode, a

delay of 2

µs is sufficient. The QT2100 reads the MOSI pin with each rising edge of SCK, and shifts data out on the

MISO pin on falling edges. The host should do the same to ensure proper operation.

Between the end of the Byte 1 shift and the start of the Byte 2 shift (and between Byte 2 and Byte 3), the host may

raise SS again, but this is not required. SS should be held high when not communicating; if SS is low this is taken as

an indication of impending communications.

In this case, extra current is drawn, as the QT2100 does not enter its lowest power sleep mode.

All timings not mentioned above should be as in

Figure 6-2 on page 33.

4.2.2

Change Pin

The QT2100 has a CHANGE output pin which allows for key state change notification. Use of the CHANGE signal

relieves the host of the burden of regularly polling the QT2100 to get key states. CHANGE goes high when an event

occurs that causes a change to the contents of the Normal Data bytes; that is, when a new key is pressed, or

released, or a movement is detected on the slider/wheel.

Similarly, when a custom threshold or LPM is sent to the QT2100, the CHANGE line is asserted to indicate that the

new setting has been applied and is shown in the Normal Exchange data.

CHANGE also goes high after a reset to indicate to the host that it should do an SPI transfer in order to provide initial

configuration information to the QT2100 (as it does on every SPI transfer).

CHANGE is driven low only once the data has been read through an SPI transfer.

In the case of a transient touch on one of the sensors, in which the touch has been removed before the host has read

the status of the sensors, the Change line remains asserted.

Note: In this case the data that will be read may be identical to the data that was previously read.

4.2.3

DRDY Pin

The Data Ready (DRDY) pin is a quick indication of the QT2100 activity. During channel acquisition bursts the pin is

held low by the device, and driven high for ~500

µs in between bursts. During processing and sleep the pin is driven

high continuously, unless a 3-byte communications exchange has taken place since the last acquisition burst.

After a 3-byte exchange has completed the pin is pulled low and remains low until the next burst completion, after

which the normal cycle resumes. This allows the host to detect if the 3-byte exchange packets have become

de-synchronized.

The QT2100 has a DRDY grace period. If communications start during the 20

µs after DRDY has been deasserted

(pulled low) by the QT2100, then DRDY is reasserted and held high until the exchange is complete. Key

measurement bursts do not take place during this time.