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AT32UC3A0512 Datasheet(PDF) 54 Page - ATMEL Corporation |
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AT32UC3A0512 Datasheet(HTML) 54 Page - ATMEL Corporation |
54 / 98 page 54 AT32UC3A Figure 12-3. SMC Signals for NRD and NRW Controlled Accesses. 12.9.1 SDRAM Signals These timings are given for 10 pF load on SDCK and 40 pF on other signals. Note: 1. The maximum frequency of the SDRAMC interface is the same as the max frequency for the HSB. NRD NCS D0 - D15 NWE A2-A25 A0/A1/NBS[3:0] SMC7 SMC19 SMC20 SMC43 SMC37 SMC42 SMC8 SMC1 SMC2 SMC23 SMC24 SMC32 SMC7 SMC8 SMC6 SMC5 SMC4 SMC3 SMC9 SMC41 SMC40 SMC39 SMC38 SMC45 SMC9 SMC6 SMC5 SMC4 SMC3 SMC33 SMC30 SMC29 SMC26 SMC25 SMC31 SMC44 Table 12-27. SDRAM Clock Signal. Symbol Parameter Max(1) Units 1/(t CPSDCK) SDRAM Controller Clock Frequency 1/(t cpcpu)MHz Table 12-28. SDRAM Clock Signal. Symbol Parameter Min Units SDRAMC1 SDCKE High before SDCK Rising Edge 7.4 ns SDRAMC2 SDCKE Low after SDCK Rising Edge 3.2 SDRAMC3 SDCKE Low before SDCK Rising Edge 7 SDRAMC4 SDCKE High after SDCK Rising Edge 2.9 SDRAMC5 SDCS Low before SDCK Rising Edge 7.5 SDRAMC6 SDCS High after SDCK Rising Edge 1.6 SDRAMC7 RAS Low before SDCK Rising Edge 7.2 SDRAMC8 RAS High after SDCK Rising Edge 2.3 SDRAMC9 SDA10 Change before SDCK Rising Edge 7.6 SDRAMC10 SDA10 Change after SDCK Rising Edge 1.9 32058KS–AVR32–01/12 |
Similar Part No. - AT32UC3A0512_14 |
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Similar Description - AT32UC3A0512_14 |
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