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AT32UC3A0512 Datasheet(PDF) 51 Page - ATMEL Corporation |
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AT32UC3A0512 Datasheet(HTML) 51 Page - ATMEL Corporation |
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51 / 98 page  51 AT32UC3A 12.9 EBI Timings These timings are given for worst case process, T = 85 ⋅C, VDDCORE = 1.65V, VDDIO = 3V and 40 pF load capacitance. Note: 1. The maximum frequency of the SMC interface is the same as the max frequency for the HSB. Note: 1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs rd hold length” or “nrd hold length”. Table 12-22. SMC Clock Signal. Symbol Parameter Max(1) Units 1/(t CPSMC) SMC Controller Clock Frequency 1/(t cpcpu)MHz Table 12-23. SMC Read Signals with Hold Settings Symbol Parameter Min Units NRD Controlled (READ_MODE = 1) SMC1 Data Setup before NRD High 12 ns SMC2 Data Hold after NRD High 0 SMC3 NRD High to NBS0/A0 Change(1) nrd hold length * t CPSMC - 1.3 SMC4 NRD High to NBS1 Change(1) nrd hold length * t CPSMC - 1.3 SMC5 NRD High to NBS2/A1 Change(1) nrd hold length * t CPSMC - 1.3 SMC6 NRD High to NBS3 Change(1) nrd hold length * t CPSMC - 1.3 SMC7 NRD High to A2 - A25 Change(1) nrd hold length * t CPSMC - 1.3 SMC8 NRD High to NCS Inactive(1) (nrd hold length - ncs rd hold length) * t CPSMC - 2.3 SMC9 NRD Pulse Width nrd pulse length * t CPSMC - 1.4 NRD Controlled (READ_MODE = 0) SMC 10 Data Setup before NCS High 11.5 ns SMC 11 Data Hold after NCS High 0 SMC 12 NCS High to NBS0/A0 Change (1) ncs rd hold length * t CPSMC - 2.3 SMC 13 NCS High to NBS0/A0 Change (1) ncs rd hold length * t CPSMC - 2.3 SMC 14 NCS High to NBS2/A1 Change (1) ncs rd hold length * t CPSMC - 2.3 SMC 15 NCS High to NBS3 Change (1) ncs rd hold length * t CPSMC - 2.3 SMC 16 NCS High to A2 - A25 Change (1) ncs rd hold length * t CPSMC - 4 SMC 17 NCS High to NRD Inactive (1) ncs rd hold length - nrd hold length)* t CPSMC - 1.3 SMC 18 NCS Pulse Width ncs rd pulse length * t CPSMC - 3.6 32058KS–AVR32–01/12 |
Similar Part No. - AT32UC3A0512_14 |
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Similar Description - AT32UC3A0512_14 |
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