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AT32UC3A0512 Datasheet(PDF) 39 Page - ATMEL Corporation |
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AT32UC3A0512 Datasheet(HTML) 39 Page - ATMEL Corporation |
39 / 98 page 39 AT32UC3A 11. Boot Sequence This chapter summarizes the boot sequence of the AT32UC3A. The behaviour after power-up is controlled by the Power Manager. For specific details, refer to Section 13. ”Power Manager (PM)” on page 53. 11.1 Starting of clocks After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the power has stabilized throughout the device. Once the power has stabilized, the device will use the internal RC Oscillator as clock source. On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have a divided frequency, all parts of the system recieves a clock with the same frequency as the internal RC Oscillator. 11.2 Fetching of initial instructions After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset address, which is 0x8000_0000. This address points to the first address in the internal Flash. The code read from the internal Flash is free to configure the system to use for example the PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals. 32058KS–AVR32–01/12 |
Similar Part No. - AT32UC3A0512_14 |
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Similar Description - AT32UC3A0512_14 |
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