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AT32UC3A0512 Datasheet(PDF) 35 Page - ATMEL Corporation |
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AT32UC3A0512 Datasheet(HTML) 35 Page - ATMEL Corporation |
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35 / 98 page  35 AT32UC3A 10.10 GPIO The GPIO open drain feature (GPIO ODMER register (Open Drain Mode Enable Register)) is not available for this device. 10.11 Peripheral overview 10.11.1 External Bus Interface • Optimized for Application Memory Space support • Integrates Two External Memory Controllers: – Static Memory Controller – SDRAM Controller • Optimized External Bus: –16-bit Data Bus – 24-bit Address Bus, Up to 16-Mbytes Addressable – Optimized pin multiplexing to reduce latencies on External Memories • 4 SRAM Chip Selects, 1SDRAM Chip Select: – Static Memory Controller on NCS0 – SDRAM Controller or Static Memory Controller on NCS1 – Static Memory Controller on NCS2 – Static Memory Controller on NCS3 10.11.2 Static Memory Controller • 4 Chip Selects Available • 64-Mbyte Address Space per Chip Select • 8-, 16-bit Data Bus • Word, Halfword, Byte Transfers • Byte Write or Byte Select Lines • Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select • Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select • Programmable Data Float Time per Chip Select • Compliant with LCD Module • External Wait Request • Automatic Switch to Slow Clock Mode • Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes 10.11.3 SDRAM Controller • Numerous Configurations Supported – 2K, 4K, 8K Row Address Memory Parts – SDRAM with Two or Four Internal Banks – SDRAM with 16-bit Data Path • Programming Facilities – Word, Half-word, Byte Access – Automatic Page Break When Memory Boundary Has Been Reached – Multibank Ping-pong Access – Timing Parameters Specified by Software – Automatic Refresh Operation, Refresh Rate is Programmable • Energy-saving Capabilities – Self-refresh, Power-down and Deep Power Modes Supported 32058KS–AVR32–01/12 |
Similar Part No. - AT32UC3A0512_14 |
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Similar Description - AT32UC3A0512_14 |
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