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AT32UC3A0512 Datasheet(PDF) 87 Page - ATMEL Corporation |
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AT32UC3A0512 Datasheet(HTML) 87 Page - ATMEL Corporation |
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87 / 98 page  87 AT32UC3A 6. CPU Cycle Counter does not reset the COUNT system register on COMPARE match. The device revision E does not reset the COUNT system register on COMPARE match. In this revision, the COUNT register is clocked by the CPU clock, so when the CPU clock stops, so does incrementing of COUNT. Fix/Workaround None. 7. Memory Protection Unit (MPU) is non functional. Fix/Workaround Do not use the MPU. 8. The following alternate GPIO function C are not available in revE MACB-WOL on GPIO9 (PA09), MACB-WOL on GPIO18 (PA18), USB-USB_ID on GPIO21 (PA21), USB-USB_VBOF on GPIO22 (PA22), and all function B and C on GPIO70 to GPIO101 (PX00 to PX39). Fix/Workaround Do not use these alternate B and C functions on the listed GPIO pins. 9. Clock connection table on Rev E Here is the table of Rev E Figure 15-1. Timer/Counter clock connections on RevE 10. Local Bus fast GPIO not available in RevE. Fix/Workaround Do not use on this silicon revision. 11. Spurious interrupt may corrupt core SR mode to exception If the rules listed in the chapter `Masking interrupt requests in peripheral modules' of the AVR32UC Technical Reference Manual are not followed, a spurious interrupt may occur. An interrupt context will be pushed onto the stack while the core SR mode will indicate an exception. A RETE instruction would then corrupt the stack.. Fix/Workaround Follow the rules of the AVR32UC Technical Reference Manual. To increase software robustness, if an exception mode is detected at the beginning of an interrupt handler, change the stack interrupt context to an exception context and issue a RETE instruction. Source Name Connection Internal TIMER_CLOCK1 32 KHz Oscillator TIMER_CLOCK2 PBA Clock / 4 TIMER_CLOCK3 PBA Clock / 8 TIMER_CLOCK4 PBA Clock / 16 TIMER_CLOCK5 PBA Clock / 32 External XC0 XC1 XC2 32058KS–AVR32–01/12 |
Similar Part No. - AT32UC3A0512_14 |
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Similar Description - AT32UC3A0512_14 |
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