HM9264B Series

Low V

Parameter

Symbol

Min

Typ

*1

Max

Unit

Test conditions

*4

V

V

DR

2.0

—

—

V

CS1

≥ V

CS2

≥ V

Data retention current

I

CCDR

—1

*1

25

*2

µAV

CS1

≥ V

or 0 V

≤ CS2 ≤ 0.2 V

Chip deselect to data

retention time

t

CDR

0

—

—

ns

See retention waveform

Operation recovery time

t

R

t

RC

*3

——ns

Notes: 1. Reference data at Ta = 25

°C.

2. 10

µA max at Ta = 0 to + 40°C.

3. t

4. CS2 controls address buffer,

WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls

data retention mode, Vin levels (address,

WE, OE, CS1, I/O) can be in the high impedance

state. If

CS1 controls data retention mode, CS2 must be CS2

≥ V

V. The other input levels (address,

WE, OE, I/O) can be in the high impedance state.

Low V

Data retention mode

CS1

≥ V

4.5 V

2.2 V

0 V

CS1

Low V

Data retention mode

CS2

≤ 0.2 V

4.5 V

0 V

CS2

0.4 V