HM9264B Series

Write Cycle

HM9264B-8L

HM9264B-10L

Parameter

Symbol

Min

Max

Min

Max

Unit

Notes

Write cycle time

t

WC

85

—

100

—

ns

Chip selection to end of write

t

CW

75

—

80

—

ns

2

Address setup time

t

AS

0—

0—

ns

3

Address valid to end of write

t

AW

75

—

80

—

ns

Write pulse width

t

WP

55

—

60

—

ns

1, 9

Write recovery time

t

WR

0—

0—

ns

4

WE to output in high-Z

t

WHZ

0

30

0

35

ns

5

Data to write time overlap

t

DW

40

—

40

—

ns

Data hold from write time

t

DH

0—

0—

ns

Output active from end of write

t

OW

5—

5—

ns

Output disable to output in high-Z

t

OHZ

0

30

0

35

ns

5

Notes: 1. A write occurs during the overlap of a low

CS1, and high CS2, and a high WE. A write begins

at the latest transition among

CS1 going low,CS2 going high and WE going low. A write ends

at the earliest transition among

CS1 going high CS2 going low and WE going high. Time t

measured from the beginning of write to the end of write.

2. t

3. t

4. t

cycle.

5. During this period, I/O pins are in the output state, therefore the input signals of the opposite

phase to the outputs must not be applied.

6. If

CS1 goes low simultaneously with WE going low after WE goes low, the outputs remain in

high impedance state.

7. Dout is the same phase of the written data in this write cycle.

8. Dout is the read data of the next address

9. In the write cycle with

OE low fixed, t

of data bus contention

t