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HM9264BLFP-10L Datasheet(PDF) 6 Page - Hitachi Semiconductor |
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HM9264BLFP-10L Datasheet(HTML) 6 Page - Hitachi Semiconductor |
6 / 14 page ![]() HM9264B Series AC Characteristics (Ta = 0 to +70 °C, V CC = 5 V ± 10%, unless otherwise noted.) Test Conditions • Input pulse levels: 0.8 V to 2.4 V • Input and output timing reference level: 1.5 V • Input rise and fall time: 10 ns • Output load: 1 TTL Gate + C L (100 pF) (Including scope & jig) Read Cycle HM9264B-8L HM9264B-10L Parameter Symbol Min Max Min Max Unit Notes Read cycle time t RC 85 — 100 — ns Address access time t AA — 85 — 100 ns Chip select access time CS1 t CO1 — 85 — 100 ns CS2 t CO2 — 85 — 100 ns Output enable to output valid t OE — 45 — 50 ns Chip selection to output in low-Z CS1 t LZ1 10 — 10 — ns 2 CS2 t LZ2 10 — 10 — ns 2 Output enable to output in low-Z t OLZ 5— 5— ns 2 Chip deselection in to output in high-Z CS1 t HZ1 0 30 0 35 ns 1, 2 CS2 t HZ2 0 30 0 35 ns 1, 2 Output disable to output in high-Z t OHZ 0 30 0 35 ns 1, 2 Output hold from address change t OH 10 — 10 — ns Notes: 1. t HZ is defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. At any given temperature and voltage condition, t HZ maximum is less than tLZ minimum both for a given device and from device to device. 3. Address must be valid prior to or simultaneously with CS1 going low or CS2 going high. |
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