LM3243

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SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013

To help minimize noise coupled back into power supplies:

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Use a star connection to route from the VBATT power input to Switcher PVIN and to VBATT_PA.

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Route traces for minimum inductance between supply pins and bypass capacitor(s).

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Route traces to minimize inductance between bypass capacitors and the ground plane.

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Maximize power supply trace inductance(s) to reduce coupling among function blocks.

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Inserting a ferrite bead in-line with power supply traces can offer a favorable tradeoff in terms of board area,

by attenuating noise that might otherwise propagate through the supply connections, allowing the use of

fewer bypass capacitors.

Manufacturing Considerations

The LM3243 package employs a 16-bump (4x4) array of 0.24 mm solder balls, with a 0.4mm pad pitch. A few

simple design rules will go a long way to ensuring a good layout.

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Pad size should be 0.225 ± 0.02 mm. Solder mask opening should be 0.325 ± 0.02 mm.

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As a thermal relief, connect to each pad with 9 mil wide, 6 mil long traces and incrementally increase each

trace to its optimal width. Symmetry is important to ensure the solder bumps re-flow evenly. Refer to TI

Application Note AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009).

LM3243 RF Evaluation Board

Figure 25. Simplified LM3243 RF Evaluation Board Schematic

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