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NCP5425DB Datasheet(PDF) 4 Page - ON Semiconductor |
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NCP5425DB Datasheet(HTML) 4 Page - ON Semiconductor |
4 / 22 page NCP5425 http://onsemi.com 4 ELECTRICAL CHARACTERISTICS (0 °C < TJ < 125°C; ROSC = 30.9 k, CCOMP1,2 = 0.1 mF, 4.75 V < VCC < 13.2 V; 10.8 V < BST < 20 V, CGATE(H)1,2 = CGATE(L)1,2 = 1.0 nF; unless otherwise specified.) Characteristic Test Condition Min Typ Max Unit ERROR AMPLIFIER VFB1 Input Bias Current VFB1 = 0 V − 0.1 1.0 mA VFB2, VREF2 Input Bias Current VFB2, VREF2 = 0.8 V − 0.1 1.0 mA Common Mode Input Voltage Range − 0.3 − 1.0 V COMP1(2) Source Current COMP1(2) = 1.2 V to 2.5 V; VFB1(2) = 0.6 V 15 30 60 mA COMP1(2) Sink Current COMP1(2) = 1.2 V; VFB1(2) = 1.0 V 15 30 60 mA Reference Voltage COMP1 = VFB1 0.792 0.800 0.808 V COMP1 Max Voltage COMP2 Max Voltage, Mode Floating COMP2 Max Voltage, Mode = 0 VFB1(2) = 0.6 V VFB1(2) = 0.6 V VFB1(2) = 0.6 V − 3.0 − 2.0 3.1 2.0 2.1 − 2.1 V COMP1(2) Min Voltage VFB1(2) = 1.2 V − 0.10 0.20 V Open Loop Gain − 95 − dB Unity Gain Bandwidth − 40 − kHz PSRR @ 1.0 kHz − 70 − dB Transconductance − − 32 − mmho Output Impedance − − 2.5 − M W GATE(H) AND GATE(L) High Voltage (AC) VCC − GATE(L)1,2 BST − GATE(H)1,2 (Note 2) − 0 0.5 V Low Voltage (AC) GATE(L)1,2 or GATE(H)1,2 (Note 2) − 0 0.5 V Rise Time 1.0 V < GATE(L)1,2 < VCC − 1.0 V 1.0 V < GATE(H)1,2 < BST − 1.0 V − 25 80 ns Fall Time VCC − 1.0 > GATE(L)1,2 > 1.0 V BST − 1.0 > GATE(H)1,2 > 1.0 V − 25 80 ns GATE(H) to GATE(L) Delay GATE(H)1,2 < 2.0 V GATE(L)1,2 > 2.0 V 20 40 80 ns GATE(L) to GATE(H) Delay GATE(L)1,2 < 2.0 V GATE(H)1,2 > 2.0 V 20 40 80 ns GATE(H)1(2) and GATE(L)1(2) Pull−Down Resistance to GND (Note 2) 50 125 280 k W PWM COMPARATOR Propagation Delay COMP1(2) = 1.0 V VFB1(2) = 0 to 1.2 V (Note 2) − 200 300 ns PWM Comparator Offset VFB1(2) = 0 V; Increase COMP1(2) until GATE(H)1(2) starts switching 0.20 0.30 0.45 V Artificial Ramp Duty Cycle = 50% 55 95 150 mV Minimum Pulse Width (Note 2) − 80 130 ns 2. Guaranteed by design, not 100% tested in production. |
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