M29W128GH70N3E datasheet(13/94 Pages) NUMONYX

Part #	M29W128GH70N3E

Description	128-Mbit (16 Mbit x8 or 8 Mbit x16, page, uniform block) 3 V supply flash memory

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Manufacturer	NUMONYX [Numonyx B.V]

Direct Link	http://www.numonyx.com

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13 / 94 page

M29W128GH, M29W128GL

Signal descriptions

13/94

2

Signal descriptions

See Figure 1: Logic diagram, and Table 2: Signal names, for a brief overview of the signals

connected to this device.

2.1

Address inputs (A0-A22)

The address inputs select the cells in the memory array to access during bus read

operations. During bus write operations they control the commands sent to the command

interface of the program/erase controller.

2.2

Data inputs/outputs (DQ0-DQ7)

The data I/O outputs the data stored at the selected address during a bus read operation.

During bus write operations they represent the commands sent to the command interface of

the internal state machine.

2.3

Data inputs/outputs (DQ8-DQ14)

The data I/O outputs the data stored at the selected address during a bus read operation

when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high

impedance. During bus write operations the command register does not use these bits.

When reading the status register these bits should be ignored.

2.4

Data inputs/outputs or address inputs (DQ15A−1)

When the device is in x 16 bus mode, this pin behaves as a data input/output pin (as DQ8-

DQ14). When the device operates in x 8 bus mode, this pin behaves as the least significant

bit of the address. Throughout the text consider references to the data input/output to

include this pin when the device operates in x 16 bus mode and references to the address

inputs to include this pin when the device operates in x 8 bus mode except when stated

explicitly otherwise.

2.5

Chip enable (E)

The chip enable pin, E, activates the memory, allowing bus read and bus write operations to

be performed. When chip enable is High, VIH, all other pins are ignored.

2.6

Output enable (G)

The output enable pin, G, controls the bus read operation of the memory.

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