5

* This specification are subject to be changed without notice.

Preliminary

Preliminary

Preliminary

Preliminary

Preliminary

EM83040A

LCD CONTROLLER

5.31.2001

RAMEN

RAMADS

RAMD(3:0)

RAMW

RAMR

A3

A2

A1

D1

D2

D3

RAM enable

RAM disable

ADDRESS

DATA

A3=address (11:8)

A2=address(7:4)

A1=address(3:0)

Ten

Tdv

Tdh

Tdd

Fig.4

address2559 ...................

address0031 ...................

address0063 ...................

address0051 ................... ..................................... ..........................

address1023 ...................

address1535 ...................

address2047 ...................

address2547 ......................................................................................................................... address2528

address2035 ......................................................................................address2019...............address2016

address1523 ............................................................address1511........................................address1504

address1011 .......................address1003 ............................................................................. address0992

LCD RAM

Area 10

Area 11

Area 9

Area 8

Area 5

Area 6

Area 7

Area 4

Area 3

Area 2

Area 1

Address 2560

Control register

Address 2560

Control register

EMPTY AREA

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

................................... address0032

address0019 ...................

s80s79s78s77

s4 s3 s2 s1

s48

s32

s16

address0011................ address7........... address0003............... address0000

COM80

COM64

COM48

COM32

COM2

COM1

Fig.5

As same as write mode , user has to sent address three times. And read data from RAM one by one which

address can be increased by internal counter. NOTE!! Be sure to make RAMR low pulse 2

µS (Tdv+data)

width and 2

µS (Tdd) high width at least.

(5) RAM mapping

RAM address is from 0 to address 2559

User fill “1” to LCD RAM , LCD driver will generate “light” waveform. Otherwise , it will generate a

“dark” waveform. The LCD RAM area is mapped to segment 1 to segment 80 from address 0 to address

19. And user can refer to fig.5 to get the idea of LCD ram mapping. The other RAM can use as general

RAM for data storage. And the RAM of address 2560 is a control register.