3

* This specification are subject to be changed without notice.

Preliminary

Preliminary

Preliminary

Preliminary

Preliminary

EM83040A

LCD CONTROLLER

5.31.2001

PIN DESCRIPTIONS

Symbol

I/O

Function

VDD

Power

GND

power

Ground

VSS3

power

EN=0 and MAIN=1, 3*regulator output, EN=1 ,VSS3=VDD

VSS2

Power

EN=0 and MAIN=1, 2*regulator output, EN=1, VSS2=VDD

MAIN

I

Master or slave control signal.

MAIN=1 ,master unit

MAIN=0 , slave unit

EN

I

This pin control whole chip power. This chip will work when this pin is

connectted to ground. And whole chip will disable when connect to VDD voltage.

EN=0 and MAIN=1 the chip will generate VSS2, VSS3, LOAD signal and internal

RC clock.

EN=1, standby mode

M1

I

Mode select

M0

I

Mode select

RAMEN

RAM read and write control signal.

1 => can not read and write. 0=> can read and write.

RAMADS

RAM data select signal

1=> RAM Data , 0=>Address

RAMW

RAM write signal, low write

RAMR

RAM read signal, low read

RAMD3~

RAM data or address bus

RAMD0

LOAD

I/O

LCD load signal between one COMMON signal to another .

MAIN=1 , the master unit will output LOAD signal.

MAIN=0 , the slave will accept the signal from master unit.

VREG

power

regulator output, connect a capacitor to ground.

CA

I

Coupling capacitor

CB

I

Coupling capacitor

V1~V5

I

Reference voltage input ,highest V1..lowest V5

O1~O80

O

LCD waveform output

FUNCTION DESCRIPTIONS

(1) User can use MAIN pin to chose master unit or slave unit.

MAIN

Unit

Function

1

MASTER

Generate these signals

Load, VSS2, VSS3, Internal RC clock

0

SLAVE

Accept these signals

Load, V1, V2, V3, V4, V5

(2) User can use M1,M2 to chose four modes. As followed

MASTER

MAIN

M1

M0

Segment

Common

Bias

Mode1

1

0

0

Reserved for test

Mode2

1

0

1

O(80:1)=C(80:1)

1/9

Mode3

1

1

0

O(32:1)=S(32:1)

O(80:33)=C(48:1)

1/7

Mode4

1

1

1

O(48;1)=S(48:1)

O(80:49)=C(32:1)

1/5