PB005802-0608

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Z85233 EMSCC™ Enhanced Mono Serial Communication Controller

automatically: transmit a flag before the data, reset

the Tx Underrun/EOM latch, force the TxD pin

high at the appropriate time when using NRZI

encoding, deassert the /RTS pin after the closing

flag, and better handle ABORTed frames when

using the 10x19 status FIFO. The combination of

these features along with the deeper data FIFOs

significantly simplifies SDLC driver software.

The CPU hardware interface has been simplified

by relieving the databus setup time requirement

and supporting the software generation of the inter-

rupt acknowledge signal (/INTACK). These

changes allow an interface with less external logic

to many microprocessor families while maintain-

ing compatibility with existing designs. I/O han-

dling of the EMSCC is improved over the SCC

with faster response of the /INT and /DTR//REQ

pins.

The many enhancements added to the EMSCC per-

mits a system design that increases overall system

performance with better data handling and less

interface logic.

All Signals with a preceding front

slash, "/", are active Low, e.g.: B//W

(WORD is active Low); /B/W (BYTE

is active Low, only).

Power connections follow conventional descrip-

tions below:

Figure 1. Z85233 Functional Block Diagram

Connection

Circuit

Device

Power

Ground

GND

Note:

Internal

Control

Logic

Channel A

Register

Channel B

Register

Interrupt

Control

Logic

CPU & DMA

Bus Interface

Databus

Control

Channel A

Channel B

/INT

/INTACK

IEI

IEO

Interrupt

Control