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IR2156STRPBF Datasheet(PDF) 18 Page - International Rectifier |
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IR2156STRPBF Datasheet(HTML) 18 Page - International Rectifier |
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18 / 21 page  IR2156(S)PbF 18 DC bus under-voltage reset are enabled when pin CPH exceeds 7.5V. Ignition Mode (IGN) The ignition mode is defined as the state the IC is in when a high voltage is being established across the lamp necessary for igniting the lamp. The IR2156 enters ignition mode when the voltage on pin CPH exceeds 13V. 5 4 5uA 6 7 CPH CT RPH RT 11 8 COM LO M2 OSC. 13 HO M1 12 VS Half Bridge Output I LOAD V BUS (+) V BUS (-) Load Return Half- Bridge Driver 1.25V S1 S4 Comp4 10 2 VCC CS R1 S3 Fault Logic RCS CCS RT RPH CT CPH Figure 4, Ignition circuitry. Pin CPH is connected internally to the gate of a p-channel MOSFET (S4) (see Figure 4) that connects pin RPH with pin RT. As pin CPH exceeds 13V, the gate-to-source voltage of MOSFET S4 begins to fall below the turn-on threshold of S4. As pin CPH continues to ramp towards VCC, switch S4 turns off slowly. This results in resistor RPH being disconnected smoothly from resistor RT, which causes the operating frequency to ramp smoothly from the preheat frequency, through the ignition frequency, to the final run frequency. The over-current threshold on pin CS will protect the ballast against a non-strike or open-filament lamp fault condition. The voltage on pin CS is defined by the lower half- bridge MOSFET current flowing through the external current sensing resistor RCS. The resistor RCS therefore programs the maximum allowable peak ignition current (and therefore peak ignition voltage) of the ballast output stage. The peak ignition current must not exceed the maximum allowable current ratings of the output stage MOSFETs. Should this voltage exceed the internal threshold of 1.3V, the IC will enter FAULT mode and both gate driver outputs HO and LO will be latched low. Run Mode (RUN) Once the lamp has successfully ignited, the ballast enters run mode. The run mode is defined as the state the IC is in when the lamp arc is established and the lamp is being driven to a given power level. The run mode oscillating frequency is determined by the timing resistor RT and timing capacitor CT (see Design Equations, page 12, Equations 3 and 4). Should hard-switching occur at the half-bridge at any time due to an open-filament or lamp removal, the voltage across the current sensing resistor, RCS, will exceed the internal threshold of 1.3 volts and the IC will enter FAULT mode. Both gate driver outputs, HO and LO, will be latched low. DC Bus Under-voltage Reset Should the DC bus decrease too low during a brown-out line condition or over-load condition, the resonant output stage to the lamp can shift near or below resonance. This can produce hard-switching at the half-bridge which can damage the half- bridge switches. To protect against this, pin VDC measures the DC bus voltage and pulls down on pin CPH linearly as the voltage on pin VDC decreases 10.9V below VCC. This causes the p- channel MOSFET S4 (Figure 4) to close as the DC bus decreases and the frequency to shift higher to a safe operating point above resonance. The DC bus level at which the frequency shifting occurs is set by the external RBUS resistor and internal RVDC resistor. By pulling down on pin CPH, the ignition ramp is also reset. Therefore, should the lamp extinguish due to very low DC bus levels, the lamp will be automatically ignited as the DC bus increases again. The internal RVDC resistor is connected between pin VDC and COM when CPH exceeds 7.5V (during preheat mode). Fault Mode (FAULT) Should the voltage at the current sensing pin, CS, exceed 1.3V at any time after the preheat mode, the IC enters fault mode and both gate driver outputs, HO and LO, are latched in the ‘low’ state. CPH is discharged to COM for resetting the preheat time, and CT is discharged to COM for disabling the oscillator. To exit fault mode, VCC must be recycled back below the UVLO negative-going turn-off threshold, or, the shutdown pin, SD, must be pulled above VSDTH+. Either of these will force the IC to enter UVLO mode (see State Diagram, page 2). Once VCC is above VCCUV+ and SD is below 4.5V, the IC will begin oscillating again in the preheat mode. |
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