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DS1820 Datasheet(PDF) 9 Page - Dallas Semiconductor |
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DS1820 Datasheet(HTML) 9 Page - Dallas Semiconductor |
9 / 27 page DS1820 030598 9/27 1–WIRE BUS SYSTEM The 1–Wire bus is a system which has a single bus mas- ter and one or more slaves. The DS1820 behaves as a slave. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1–Wire signaling (signal types and tim- ing). HARDWARE CONFIGURATION The 1–Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1–Wire bus must have open drain or 3–state outputs. The 1–Wire port of the DS1820 (I/O pin) is open drain with an internal circuit equivalent to that shown in Figure 9. A multidrop bus consists of a 1–Wire bus with multiple slaves attached. The 1–Wire bus requires a pullup resistor of approximately 5K Ω. HARDWARE CONFIGURATION Figure 9 +5V 4.7K RX TX RX TX 1OO OHM MOSFET DS1820 1–WIRE PORT BUS MASTER 5 µA Typ. RX = RECEIVE TX = TRANSMIT The idle state for the 1–Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1–Wire bus is in the inactive (high) state during the re- covery period. If this does not occur and the bus is left low for more than 480 µs, all components on the bus will be reset. TRANSACTION SEQUENCE The protocol for accessing the DS1820 via the 1–Wire port is as follows: • Initialization • ROM Function Command • Memory Function Command • Transaction/Data INITIALIZATION All transactions on the 1–Wire bus begin with an initial- ization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS1820 is on the bus and is ready to operate. For more details, see the “1–Wire Signaling” section. ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the five ROM function commands. All ROM function commands are 8–bits long. A list of these com- mands follows (refer to flowchart in Figure 6): |
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