CS43L43-KZ datasheet(31/36 Pages) CIRRUS

Part #	CS43L43-KZ

Description	Low Voltage,Stereo DAC With Headphone Amp

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Manufacturer	CIRRUS [Cirrus Logic]

Direct Link	http://www.cirrus.com

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31 / 36 page

CS43L43

DS479PP3

31

SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK (Inputs: Logic “0” =

GND, Logic “1” = VL.)

Notes: 6. In Internal SCLK Mode, the LRCK duty cycle must be 50%

+/− 1/2 MCLK Period.

Parameters

Symbol

Min

Typ

Max

Units

Internal SCLK Mode

LRCK Duty Cycle

(Note 6)

-50

-

%

SCLK Period

tsclkw

--

s

SCLK rising to LRCK edge

tsclkr

--

s

SDATA valid to SCLK rising setup time

tsdlrs

--

ns

SCLK rising to SDATA hold time

Single-Speed Mode

tsdh

--

ns

Double-Speed Mode

tsdh

--

ns

1

SCLK

-----------------

tsclkw

2

------------------

1

512

()Fs

----------------------10

+

1

512

()Fs

----------------------15

+

1

384

(

)Fs

----------------------15

+

Figure 20. Internal Serial

Mode Input Timing

*The SCLK pulses shown are internal to the CS43L43.

SD A T A

*IN T E R N A L

SC L K

LR C K

sc lk w

t

sd lrs

t

sdh

t

sc lk r

t

SD A TA

LR C K

MC LK

*INT E R NA L S C LK

1

N

2

N

Figure 21. Internal Serial Clock Generation

* The SCLK pulses shown are internal to the CS43L43.

N equals MCLK divided by SCLK

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CS43L43-KZ Datasheet(PDF) 31 Page - Cirrus Logic

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