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CS43L43-KZ Datasheet(PDF) 24 Page - Cirrus Logic

Part # CS43L43-KZ
Description  Low Voltage,Stereo DAC With Headphone Amp
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43L43-KZ Datasheet(HTML) 24 Page - Cirrus Logic

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CS43L43
24
DS479PP3
5.11 MODE CONTROL 2 (ADDRESS 0BH)
5.11.1 MASTER CLOCK DIVIDE ENABLE (MCLKDIV) BIT 7
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other
internal circuitry.
NOTE: Internal SCLK is not available when this function is enabled.
5.11.2 DIGITAL INTERFACE FORMAT (DIF) BIT 0-2
Default = 000 - Format 0 (I2S, up to 24-bit data, 64 x Fs Internal SLCK)
Function:
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in Figures 2-4.
NOTE: Internal SCLK is not available when MCLKDIV is enabled.
7
654
32
10
MCLKDIV
RESERVED
RESERVED
RESERVED
RESERVED
DIF2
DIF1
DIF0
0
000
00
00
DIF2
DIF1
DIF0
DESCRIPTION
Format
FIGURE
000
I2S, up to 24-bit data, 64 x Fs Internal SLCK
0
2
001
I2S, up to 16-bit data, 32 x Fs Internal SLCK
1
2
0
1
0
Left Justified, up to 24-bit data,
2
3
0
1
1
Right Justified, 24-bit data
3
4
1
0
0
Right Justified, 20-bit data
4
4
1
0
1
Right Justified, 16-bit data
5
4
1
1
0
Right Justified, 18-bit data
6
4
1
1
1
Identical to Format 1
1
2
Table 14. Digital Interface Format - Control Port Mode


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