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CS43L43-KZ Datasheet(PDF) 10 Page - Cirrus Logic |
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CS43L43-KZ Datasheet(HTML) 10 Page - Cirrus Logic |
10 / 36 page ![]() CS43L43 10 DS479PP3 3.6.1 Power-up When the device is initially powered-up, the audio outputs, HP_A and HP_B, are clamped to GND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the qui- escent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output be- gins. This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, minimizing the power-up transient. 3.6.2 Power-down To prevent transients at power-down, the device must first enter its power-down state by setting the RST pin low. When this occurs, audio output ceases and the internal output buffers are disconnected from HP_A and HP_B. In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on. 3.6.3 Discharge Time To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before turning on the power or exiting the power-down state. If full discharge does not occur, a tran- sient will occur when the audio outputs are initially clamped to GND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance and the output load. For example, with a 220 µF capacitor and a 16 Ω load, the minimum power-down time will be approximately 0.4 seconds. |
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