CS43L43

6

DS479PP3

3.0 APPLICATIONS

3.1 Sample Rate Range/Operational Mode Select

The device operates in one of two operational modes. Operation in either mode depends on the input sam-

ple rate and the ratio of the master clock to the left/right clock (see section 3.2). Sample rates outside the

specified range for each mode are not supported.

3.2 System Clocking

The device requires external generation of the master (MCLK) and left/right (LRCK) clocks. The device

also requires external generation of the serial clock (SCLK) if the internal serial clock is not used. The

specified ratios. The specified ratios of MCLK to LRCK, along with several standard audio sample rates

and the required MCLK frequency, are illustrated in Tables 2-3.

*Requires MCLKDIV bit = 1 in the Mode Control 2 register (address 0Bh).

2kHz - 50kHz

Single Speed Mode

50kHz - 100kHz

Double Speed Mode

Table 1. CS43L43 Operational Mode

Sample Rate

(kHz)

MCLK (MHz)

256x

384x

512x

768x*

1024x*

32

8.1920

12.2880

16.3840

24.5760

32.768

44.1

11.2896

16.9344

22.5792

33.8688

45.1584

48

12.2880

18.4320

24.5760

36.8640

49.1520

Table 2. Single-Speed Mode Standard Frequencies

Sample Rate

(kHz)

MCLK (MHz)

128x

192x

256x*

384x*

64

8.1920

12.2880

16.3840

24.5760

88.2

11.2896

16.9344

22.5792

33.8688

96

12.2880

18.4320

24.5760

36.8640

Table 3. Double-Speed Mode Standard Frequencies