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CS8412 Datasheet(PDF) 4 Page - Cirrus Logic |
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CS8412 Datasheet(HTML) 4 Page - Cirrus Logic |
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4 / 36 page  CS4327 4 DS190F1 SWITCHING CHARACTERISTICS (T A = 25 °C; VA+ = 5.0 V; Inputs: Logic 0 = 0 V, Logic 1 = VD+, CL = 20 pF) Parameter Symbol Min Typ Max Unit Input Sample Rate Fs 1 - 50 kHz MCLK Pulse Width High MCLK/LRCK = 512 10 - - ns MCLK Pulse Width Low MCLK/LRCK = 512 10 - - ns MCLK Pulse Width High MCLK/LRCK = 384 21 - - ns MCLK Pulse Width Low MCLK/LRCK = 384 21 - - ns MCLK Pulse Width High MCLK/LRCK = 256 31 - - ns MCLK Pulse Width Low MCLK/LRCK = 256 31 - - ns External SCLK Mode SCLK Pulse Width Low tsclkl 20 - - ns SCLK Pulse Width High tsclkh 20 - - ns SCLK Period tsclkw -- ns SCLK rising to LRCK edge delay tslrd 20 - - ns SCLK rising to LRCK edge setup time tslrs 20 - - ns SDATA valid to SCLK rising setup time tsdlrs 20 - - ns SCLK rising to SDATA hold time tsdh 20 - - ns Internal SCLK Mode SCLK Period SCLK/LRCK = 64 tsclkw -- ns SCLK rising to LRCK edge tsclkr -- ns SDATA valid to SCLK rising setup time tsdlrs -- ns SCLK rising to SDATA hold time MCLK/LRCK = 256 or 512 tsdh -- ns SCLK rising to SDATA hold time MCLK/LRCK = 384 tsdh -- ns 1 128(Fs) -------------------- 1 64(Fs) ----------------- t sc lk w 2 ------------------ 1 512(Fs) -------------------- 10 + 1 512(Fs) -------------------- 15 + 1 384(Fs) -------------------- 15 + |
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