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CS8412 Datasheet(PDF) 23 Page - Cirrus Logic |
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CS8412 Datasheet(HTML) 23 Page - Cirrus Logic |
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23 / 36 page  Input/Output for Clocks and Data The evaluation board has been designed to allow the interface to external systems via the 10-pin header, J1. This header allows the evaluation board to accept externally generated clocks and data. The schematic for the clock/data I/O is shown in Figure 6. The 74HC243 transceiver functions as an I/O buffer where the CLK SOURCE jumper determines if the transceiver operates as a transmitter or receiver. The transceiver operates as a transmitter with the CLK SOURCE jumper in the 8412 position. LRCK, SDATA, and SCLK from the CS8412 will be available on J1. J22 must be in the 0 position and J23 must be in the 1 position for MCLK to be an output and to avoid bus conten- tion on MCLK. The transceiver operates as a receiver with the CLK SOURCE jumper in the EXTERNAL posi- tion. LRCK, SDATA and SCLK on J1 become inputs. The CS8412 must be removed from the evaluation board for operation in this mode. There are 2 options for the source of MCLK in the EXT CLK source mode. MCLK can be an input with J23 in the 1 position and J22 in the 0 position. However, the recommended mode of operation is to generate MCLK on the evaluation board. MCLK becomes an output with LRCK, SCLK and SDATA inputs. This technique insures that the CS4327 receives a jitter free clock to maximize performance. This can be accom- plished by installing a crystal oscillator into U4, see Figure 8 (the socket for U4 is located within the footprint for the CS8412) and placing J22 in the 1 position and J23 in the 0 position. Analog Filter The design of the second-order Butterworth low- pass filter, Figure 5, is discussed in the CS4327 data sheet and the applications note "Design Notes for a 2-pole Filter." Grounding and Power Supply Decoupling The CS4327 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 2 shows the recommended power arrangements with VA+ connected to a clean +5 Volt supply. VD1+ is derived from VA+ through a 2 ohm resistor. VD1+ should not used for any additional digital circuitry. Ideally, all mode pins which require VD1+ should be connected to pin 6 of the CS4327 and all mode pins which require DGND should con- nected to pin 5 of the CS4327. AGND and DGND, Pins 4 and 5, are connected together at the CS4327. The evaluation board has separate analog and digital regions with individual ground planes. DGND for the CS4327 should not be confused with the ground for the digital section of the system (GND). The CS4327 is po- sitioned over the analog ground plane near the digital/analog ground plane split. These ground planes are connected elsewhere on the board. This layout technique is used to minimizing digi- tal noise and to insure proper power supply matching/sequencing. The decoupling capacitors are located as close to the CS4327 as possible. Extensive use of ground plane fill on both the analog and digital sections of the evaluation board yield large reductions in radiated noise ef- fects. CDB4327 DS190DB1 23 |
Similar Part No. - CS8412 |
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Similar Description - CS8412 |
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