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CS8412 Datasheet(PDF) 22 Page - Cirrus Logic |
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CS8412 Datasheet(HTML) 22 Page - Cirrus Logic |
22 / 36 page CDB4327 System Overview The CDB4327 evaluation board is an excellent means of quickly evaluating the CS4327. The CS8412 digital audio interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio test equip- ment. The evaluation board also allows the user to supply clocks and data through a 10-pin header for system development. The CDB4327 schematic has been partitioned into 7 schematics shown in Figures 2 through 8. Each partitioned schematic is represented in the system diagram shown in Figure 1. Notice that the the system diagram also includes the inter- connections between the partitioned schematics. CS4327 Digital to Analog Converter A description of the CS4327 is included in the CS4327 data sheet. CS8412 Digital Audio Receiver The system receives and decodes the standard S/PDIF data format using a CS8412 Digital Audio Receiver, Figure 8. The outputs of the CS8412 include a serial bit clock, serial data, left-right clock (FSYNC), de-emphasis control and a 256Fs master clock. The operation of the CS8412 and a discussion of the digital audio in- te rface a re inc lud ed in t he 19 94 Crystal Semiconductor Audio Data Book. During normal operation, the CS8412 operates in the Channel Status mode where the LED’s dis- play channel status information for the channel selected by the CSLR/FCK jumper. This allows the CS8412 to decode and supply the de-empha- sis bit from the digital audio interface for control of the CS4327 de-emphasis filter via pin 3, CC/F0, of the CS8412. When the Error Information Switch is activated, the CS8412 operates in the Error and Frequency information mode. The information displayed by the LED’s can be decoded by consulting the CS8412 data sheet. If the Error Information Switch is activated, the CC/F0 output has no re- lation to the de-emphasis bit and it is likely that the de-emphasis control for the CS4327 will be erroneous and produce an incorrect audio output. Encoded sample frequency information can be displayed provided a proper clock is being ap- plied to the FCK pin of the CS8412. When an LED is lit, this indicates a "1" on the corre- sponding pin located on the CS8412. When an LED is off, this indicates a "0" on the corre- sponding pin. Neither the L or R option of CSLR/FCK should be selected if the FCK pin is being driven by a clock signal. The evaluation board has been designed such that the input can be either optical or coax, Fig- ure 7. It is not necessary to select the active input. However, both inputs can not be driven simultaneously. Data Format The CS4327 must be configured to be compat- ible with the incoming data and can be set with DIF0 and DIF1. The CS8412 data format can be set with the M0, M1, M2 and M3. There are sev- eral data formats which the CS8412 can produce that are compatible with CS4327. Refer to Table 2 for one possibility. Power Supply Circuitry Power is supplied to the evaluation board by four binding posts, Figure 9. The +5 Volt input supplies power to the CS4327 (through VA+), the CS8412 (through VA+ and VD+), and the +5 Volt digital circuitry (through VD+). The +/- 12 Volt input supplies power to the analog filter cir- cuitry. CDB4327 22 DS190DB1 |
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