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S80L186EB16 Datasheet(PDF) 27 Page - InnovASIC, Inc |
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S80L186EB16 Datasheet(HTML) 27 Page - InnovASIC, Inc |
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27 / 85 page  IA186EB/IA188EB Data Sheet 8-Bit/16-Bit Microcontrollers July 10, 2011 IA211080314-13 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 27 of 85 1-888-824-4184 Table 7. IA186EB Pin/Signal Descriptions (Continued) Signal Pin Description Name PLCC LQFP PQFP clkin clkin 41 28 71 clock input. Input. The clkin pin is the input connection for an external clock. An external oscillator operating at two times the required processor operating frequency can be connected to this pin. If a crystal is used to supply the clock, it is connected between the clkin pin and the oscout pin (see oscout table entry). When a crystal is connected, it drives an internal Pierce oscillator to the IA186EB. clkout clkout 44 31 74 clock output. Output. The clkout pin provides a timing reference for inputs and outputs of the IA186EB. This clock output is one-half the input clock (clkin) frequency. The clkout signal has a 50% duty cycle, transitioning every falling edge of clkin. cts0_n cts0_n 51 38 1 clear to send, Serial Port 0. Input. Active Low. When this input is high (i.e., not asserted), data transmission from Serial Port 0 is inhibited. When the signal is asserted (low), data transmission is permitted. cts1_n p2.4/cts1_n 56 43 6 clear to send, Serial Port 1. Input. Active Low. When this input is high (i.e., not asserted), data transmission from Serial Port 1 is inhibited. When the signal is asserted (low), data transmission is permitted. den_n den_n 11 80 43 data enable. Output. Active Low. This signal is used to enable of bidirectional transceivers in a buffered system. The den_n signal is asserted (low) only when data is to be transferred on the bus. dt/r_n dt/r_n 16 NA NA data transmit/receive. Output. This signal is used to control the direction of data flow for bidirectional buffers in a buffered system. When dt/r_n is high, the direction indicated is transmit; when dt/t_n is low, the direction indicated is receive. error_n error_n 3 NA NA error. Input. Active Low. When this signal is asserted (low), it indicates that the last numerics coprocessor operation resulted in an exception condition. |
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