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AT49BV/LV4096A

1618H–FLASH–4/04

AT49BV/LV4096A SOIC (SOP)

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VPP

NC

A17

A7

A6

A5

A4

A3

A2

A1

A0

CE

GND

OE

I/O0

I/O8

I/O1

I/O9

I/O2

I/O10

I/O3

I/O11

RESET

WE

A8

A9

A10

A11

A12

A13

A14

A15

A16

BYTE

GND

I/O15/A-1

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

AT49BV/LV4096A TSOP Top View

Type 1

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A15

A14

A13

A12

A11

A10

A9

A8

NC

NC

WE

RESET

VPP

NC

NC

NC

A17

A7

A6

A5

A4

A3

A2

A1

A16

BYTE

GND

I/O15/A-1

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

OE

GND

CE

A0

The device is erased by executing the Erase command sequence; the device internally

controls the erase operation. The memory is divided into four blocks for erase opera-

tions. There are two 4K word parameter block sections, the boot block, and the main

memory array block. The typical number of program and erase cycles is in excess of

10,000 cycles.

The 8K word boot block section includes a reprogramming lock out feature to provide

data integrity. This feature is enabled by a command sequence. Once the boot block

programming lockout feature is enabled, the data in the boot block cannot be changed

when input levels of 5.5 volts or less are used. The boot sector is designed to contain

user secure code.

The BYTE pin controls whether the device data I/O pins operate in the byte or word

configuration. If the BYTE pin is set at a logic “1” or left open, the device is in word con-

figuration, I/O0 - I/O15 are active and controlled by CE and OE.

If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O

pins I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14

are tri-stated and the I/O15 pin is used as an input for the LSB (A-1) address function.