© 2000 California Micro Devices Corp. All rights reserved.

6/16/2000

5

CM88L70/70C

CALIFORNIA MICRO DEVICES

215 Topaz Street, Milpitas, California 95035

Tel: (408) 263-3214

Fax: (408) 263-7846

www.calmicro.com

Functional Description

The CAMD CM88L70/70C DTMF Integrated Receiver provides the

design engineer with not only low power consumption, but high

performance in a small 18-pin DIP, SOIC, or 20-pin PLCC, TSSOP, or

QSOP package configuration. The CM88L70/70C’s internal

architecture consists of a bandsplit filter section which separates the

high and low tones of the received pair, followed by a digital decode

(counting) section which verifies both the frequency and duration of

the received tones before passing the resultant 4-bit code to the output

bus.

Filter Section

Separation of the low-group and high-group tones is achieved by

capacitor bandpass filters. The bandwidths of these filters correspond

to the bands enclosing the low-group and high-group tones (See

Figure 3). The filter section also incorporates notches at 350 Hz and

440 Hz which provides excellent dial tone rejection. Each filter output

is followed by a single order switched capacitor section which smooths

the signals prior to limiting. Signal limiting is performed by high-gain

comparators. These comparators are provided with a hysteresis to

prevent detection of unwanted low-level signals and noise. The

outputs of the comparators provide full-rail logic swings at the

frequencies of the incoming tones.

Decoder Section

The CM88L70/70C decoder uses a digital counting technique to

determine the frequencies of the limited tones and to verify that these

tones correspond to standard DTMF frequencies. A complex averaging

algorithm is used to protect against tone simulation by extraneous

signals (such as voice) while providing tolerance to small frequency

variations. The averaging algorithm has been developed to ensure

an optimum combination of immunity to “talk-off” and tolerance to

the presence of interfering signals (third tones) and noise. When the

detector recognizes the simultaneous presence of two valid tones

(known as “signal condition”), it raises the “Early Steering” flag (ESt).

Any subsequent loss of signal condition will cause ESt to fall.

Steering Circuit

Before the registration of a decoded tone pair, the receiver checks for

a valid signal duration (referred to as “character-recognition-

condition”). This check is performed by an external RC time constant

the capacitor discharges. Providing signal condition is maintained

latching its corresponding 4-bit code (See Figure 2) into the output

GT continues to drive high as long as ESt remains high, signaling that

a received tone pair has been registered. The contents of the output

latch are made available on the 4-bit output bus by raising the three-

state control input (TOE) to a logic high. The steering circuit works in

reverse to validate the interdigit pause between signals. Thus, as well

as rejecting signals too short to be considered valid, the receiver will

tolerate signal interruptions (drop outs) too short to be considered a

valid pause. This capability together with the capability of selecting

the steering time constants externally, allows the designer

to tailor

performance to meet a wide variety of system requirements.

Guard Time Adjustment

In situations which do not require independent selection of receive

and pause, the simple steering circuit of Figure 4 is applicable.

Component values are chosen according to the following formula:

signal duration to be recognized by the receiver. A value for C of 0.1

uF is recommended for most applications, leaving R to be selected by

milliseconds would be 300K. A typical circuit using this steering

configuration is shown in Figure 1. The timing requirements for most

telecommunication applications are satisfied with this circuit. Different

steering arrangements may be used to select independently the

be necessary to meet system specifications which place both accept

and reject limits on both tone duration and interdigit pause.

Guard time adjustment also allows the designer to tailor system

improves talk-off performance, since it reduces the probability that

tones simulated by speech will maintain signal condition for long

where fast acquisition time and immunity to drop-outs would be

requirements. Design information for guard time adjustment is shown

in Figure 5.

Input Configuration

The input arrangement of the CM88L70/70C provides a differential

used to bias the inputs at mid-rail.

Provision is made for connection of a feedback resistor to the op-

amp output (GS) for adjustment of gain.

In a single-ended configuration, the input pins are connected as shown

in Figure 1, with the op-amp connected for unity gain and VREF biasing

which permits the adjustment of gain with the feedback resistor R5.

Clock Circuit

The internal clock circuit is completed with the addition of a standard

television color burst crystal or ceramic resonator having a resonant

frequency of 3.579545 MHz. The CM8870C in a PLCC package has

a buffered oscillator output (OSC3) that can be used to drive clock

inputs of other devices such as a microprocessor or other CM887X’s

as shown in Figure 7. Multiple CM88L70/70Cs can be connected as

shown in figure 8 such that only one crystal or resonator is required.

Power Down and Inhibit Mode

A logic high applied to pin 6 (PD) will power down the device to

minimize the power consumption in a standby mode. It stops the

oscillator and functions of the filters.

Inhibit mode is enabled by a logic high input to the pin 5 (INH). It

inhibits the detection of tones representing characters A, B, C and

D. The output code will remain the same as the previous detected

code (see Figure 2).